Conductive plugs have become an accepted and manufacturable means for electrically connecting metal layers of a semiconductor device to underlying conductive members (such as diffusion regions, polysilicon layers, or other metal layers), especially in 0.35 .mu.m manufacturing technology. Probably the most popular form of conductive plug used in semiconductor manufacturing is a tungsten plug. However, tungsten is dissimilar to the most commonly used metal in semiconductor devices, aluminum. Due to the material dissimilarities, the combination of tungsten plugs with aluminum metal interconnects raises some concerns. For example, problems associated with electromigration and defectivities have been reported or observed in using tungsten plugs in conjunction with aluminum interconnects. Apart from reliability and performance concerns, the use of tungsten plugs is disfavored due to its process complexity. In addition to depositing tungsten to form the plug, layers such as titanium and titanium nitride are often needed to serve as adhesion promoters and diffusion barriers.
For these reasons, it is desirable to have plugs made of the same material as the interconnect, resulting in a "monolithic interconnect." Apart from improved reliability, structures which use monolithic interconnects, wherein the metal serves as both the interconnect itself and as the conductive plug, stud, or via to connect to underlying conductive members have been proposed. See, for example, "Dual Damascene: A ULSI Wiring Technology," by C. W. Kaanta, appearing in the proceedings of the June, 1991 VLSI Multilevel Interconnect Conference. In almost all monolithic interconnects which have been proposed, chemical mechanical polishing (CMP) is utilized to etch or polish back a blanket layer of metal, leaving metal only in recessed or trenched areas of the underlying substrate. The left over metal is often referred to as an inlaid interconnect, meaning that the interconnect metal has been laid into the surrounding dielectric layer as opposed to the dielectric layer being formed around the metal interconnect.
A problem has arisen in the use of CMP to form inlaid interconnects, particularly those formed of aluminum. The problem is sometimes referred to as "dishing" or "cusping." An example of the problem is illustrated in FIG. 1, which is a cross-sectional illustration of a portion of a semiconductor device 10. Semiconductor device 10 includes a semiconductor substrate 12 having an overlying dielectric layer 14. As an example, semiconductor substrate 12 is a silicon wafer having an overlying silicon dioxide layer. Within dielectric layer 14, an opening 16 has been etched. After etching opening 16, a blanket layer of metal, such as aluminum, is deposited over device 10, and subsequently polished back to remove portions of the aluminum which lie beyond opening 16. Upon polishing, the only portion of the aluminum which remains in device 10 is that which is within opening 16. The metal remaining within opening 16 forms an interconnect 18. As is evident from FIG. 1, interconnect 18 is not planar with the surrounding dielectric layer 14. Instead, interconnect 18 is slightly recessed within the opening, creating a dishing or cusping effect. The dishing phenomenon is particularly apparent when the width of opening 16 is relatively large, for example greater than one micron. The dishing effect observed in the inlaid interconnect is problematic because the recession in the device typography is replicated to subsequent layers deposited upon device 10.
One way to avoid the dishing problem is to eliminate large metal structures (for example greater than one micron in width) from the device. However, this is not a practical solution because, for example, the device requires metal bond pads which occupy relatively large areas.
In view of the desirability for a semiconductor manufacturer to form monolithic or inlaid interconnects, a need exists for a method to form such interconnects without some of the problems associated with prior attempts, such as the problem of dishing.